This article explains design and implementation of a Special Purpose Processor on FPGA. Source files can be accessed at here.

Introduction

In this project I designed a special purpose processor that computes absolute difference of two 8-bit unsigned integers. Firstly, I designed ALU and Register Block (RB) components according to the definition given to me. Then, I designed an algorithm that I can implement using functions in my custom ALU alone. I draw algorithmic state machine diagram of my algorithm according to Moore machine model. I constructed my Control Unit (CU) component with behavioural architecture. Behavior of the machine for all possible state codes are determined. Proper test-bench code is written and behavioural simulation is performed. Waformes generated by the behavoral simulation are included in the project report. Finally, the project is synthesized and implemented. Timing and utilization reports are generated and included in the project report. RTL scheme of the design is also included. Algorithmic State Machine

Explanation

Absolute difference operation basically consists of subtraction and a comparing with zero. Subtraction of integers is performed using two’s complement arithmetic. First, negative of the second operand is obtained by getting its bitwise complement then incrementing it. I achieved to obtain bitwise complement operation utilizing XOR operator existing inside my custom ALU. I received result from XOR operation with 0xFF constant value to perform complement operation. Then, I addend the constant value 0x01 in order to increment it. I short-circuited the answer of absolute difference to the first operand itself when the second operand becomes zero. In order to do this, I checked the zero flag after addition operation, and inserted a jump command towards output state conditioned with high-value zero flag case. After this process, I added resulting negative of the second operand with the first operand. Following the mentioned summation, I checked carry flag to determine sign of the sum. Then a jump instruction is executed with destination to output instruction state when the carry flag is zero. Otherwise, the sum is negated in order to make it positive valued. Finally, the result is written to output port to be read from outside.

Waveforms

RTL Scheme

Implementation Reports

Timing Report Utilization Report